A novel deep submicron low power bus coding technique

Day by Day as the technology is shrinking and as chip density and frequency are increasing, power dissipation on data bus has become the most predominant factor than the power dissipation in other part of the circuitry. Further de facto, the inter-wire capacitance becomes a dominating factor in proliferating Deep Submicron Technology (DSM) compared to substrate capacitance. So, the earlier schemes minimizing the substrate capacitances are not valid in these buses. By taking these facts into account a novel bus coding technique is proposed in this paper which reduces the inter-wire capacitance by 13 % to 15% for 8, 16 and 32 bit bus compared to if the data sent unencoded. The proposed method considers two grouping of the bus lines and selects that grouping which yields the minimum inter-wire capacitance.